// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module frame_fmt_conv 
(
    input  wire          I_sclk,
    //
    input  wire          I_v_start,
    input  wire          I_hs,
    input  wire [  7: 0] I_data,
    input  wire [ 10: 0] I_h_num,
    // to led_display_top
    output reg           O_frame_start,
    output wire          O_frame_end,
    output reg           O_row_end,
    output reg           O_burst_start,
    output reg  [ 10: 0] O_burst_row,
    output wire [ 10: 0] O_burst_col,
    output reg           O_pixel_en,
    output reg  [  7: 0] O_pixel_data
);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  hs;
reg  hs_dly;
reg  [  7: 0] data;
reg  [  7: 0] data_dly;
reg  row_end;
reg  row_end_dly1;
reg  row_end_dly2;

/******************************************************************************
                                <module body>
******************************************************************************/
assign O_frame_end = 1'b0;
assign O_burst_col = 'd0;

always @(posedge I_sclk)
    O_frame_start <= I_v_start;

always @(posedge I_sclk)
    begin
    hs <= I_hs;
    data <= I_data;
    hs_dly <= hs;
    data_dly <= data;
    end

always @(posedge I_sclk)
    begin
    O_burst_start <= I_hs && !hs;
    row_end <= !I_hs && hs;
    row_end_dly1 <= row_end;
    row_end_dly2 <= row_end_dly1;
    O_row_end <= row_end_dly2;
    end

always @(posedge I_sclk)
    if (I_v_start)
        O_burst_row <= 'd0;
    else if (O_row_end)
        O_burst_row <= O_burst_row + 1'b1;

always @(posedge I_sclk)
    begin
    O_pixel_en <= hs_dly;
    O_pixel_data <= data_dly;
    end
    
endmodule
`default_nettype wire

